View CY62167ELL-45ZXIT_8659317.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy62167e mobl ? 16-mbit (1 m 16 / 2 m 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-15607 rev. *e revised august 22, 2013 16-mbit (1 m 16 / 2 m 8) static ram features configurable as 1 m 16 or as 2 m 8 sram very high speed: 45 ns wide voltage range: 4.5 v to 5.5 v ultra low standby power ? typical standby current: 1.5 a ? maximum standby current: 12 a ultra low active power ? typical active current: 2.2 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2 , and oe features automatic power-down when deselected cmos for optimum speed and power offered in 48-pin tsop i package functional description the cy62167e is a high performance cmos static ram organized as 1 m words by 16-bits/2 m words by 8-bits. this device features advanced circuit design to provide an ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications. the device also has an automatic power down feature t hat reduces power consumption when addresses are not toggling. place the device into standby mode when deselected (ce 1 high, or ce 2 low, or both bhe and ble are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: the device is deselected (ce 1 high or ce 2 low) outputs are disabled (oe high) both byte high enable and byte low enable are disabled (bhe , ble high) or a write operation is in progress (ce 1 low, ce 2 high, and we low) to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location spec ified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from the i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device , take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see truth table on page 12 for a complete description of read and write modes. the cy62167e device is suitable for interfacing with processors that have ttl i/p levels. it is not suitable for processors that require cmos i/p levels. please see electrical characteristics on page 4 for more details and suggested alternatives. 1 m 16 / 2 m 8 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 power down circuit bhe ble ce 2 ce 1 ce 2 ce 1 byte a 19 logic block diagram
cy62167e mobl ? document number: 001-15607 rev. *e page 2 of 17 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 12 ordering information ...................................................... 13 ordering code definitions ..... .................................... 13 package diagram ............................................................ 14 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc? solutions ...................................................... 17 cypress developer community ................................. 17 technical support ................. .................................... 17
cy62167e mobl ? document number: 001-15607 rev. *e page 3 of 17 pin configuration 48-pin tsop i pinout ( top view) [1, 2] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we ce 2 nc bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss i/o15/a20 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe vss ce1 a0 product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max cy62167ell 4.5 5.0 5.5 45 2.2 4.0 25 30 1.5 12 notes 1. nc pins are not connected on the die. 2. the byte pin in the 48-pin tsopi package must be tied to v cc to use the device as a 1 m 16 sram. the 48-tsopi package can also be used as a 2 m 8 sram by tying the byte signal to v ss . in the 2 m 8 configuration, pin 45 is a20, while bhe , ble and i/o 8 to i/o 14 pins are not used. 3. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
cy62167e mobl ? document number: 001-15607 rev. *e page 4 of 17 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential .................................... .....................?0.5 v to 6.0 v dc voltage applied to outputs in high z state [4, 5] .........................................?0.5 v to 6.0 v dc input voltage [4, 5] .....................................?0.5 v to 6.0 v output current into outputs (low) ............................. 20 ma static discharge voltage (mil-std-883, method 3015) ................................. >2001 v latch-up current ..................................................... >200 ma operating range device range ambient temperature v cc [6] cy62167ell industrial ?40 c to +85 c 4.5 v to 5.5 v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [7] max v oh output high voltage v cc = 4.5 v i oh = ?1.0 ma 2.4 ? ? v v cc = 5.5 v i oh = ?0.1 ma ? ? 3.4 [8] v ol output low voltage i ol = 2.1 ma ? ? 0.4 v v ih input high voltage v cc = 4.5 v to 5.5 v 2.2 ? v cc + 0.5 v v v il input low voltage v cc = 4.5 v to 5.5 v ?0.5 ? 0.7 [9] v i ix input leakage current gnd < v i < v cc ?1 ? +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?2530ma f = 1 mhz ? 2.2 4.0 ma i sb2 [10] automatic power down current?cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, or bhe and ble > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc (max) ? 1.5 12 a notes 4. v il (min) = ?2.0 v for pulse durations less than 20 ns. 5. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 6. full device ac operation is based on a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25 c. 8. please note that the maximum voh limit doesnot exceed minimum cmos vih of 3.5 v. if you are interfacing this sram with 5 v le gacy processors that require a minimum vih of 3.5v, please refer to application note an6081 for technical details and options you may consider. 9. under dc conditions the device meets a v il of 0.8 v. however, in dynamic conditions input low voltage applied to the device must not be higher than 0.7 v. 10. chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating.
cy62167e mobl ? document number: 001-15607 rev. *e page 5 of 17 capacitance parameter [11] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [11] description test conditions 48-pin tsop i unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 60 ? c/w ? jc thermal resistance (junction to case) 4.3 ? c/w ac test loads and waveforms figure 1. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time= 1 v/ns fall time= 1 v/ns output v equivalent to: thvenin equivalent all input pulses r th r1 parameters values unit r1 1800 ? r2 990 ? r th 639 ? v th 1.77 v note 11. tested initially and after any design or proc ess changes that may affect these parameters.
cy62167e mobl ? document number: 001-15607 rev. *e page 6 of 17 data retention characteristics over the operating range parameter description conditions min typ [12] max unit v dr v cc for data retention ? 2.0 ? ? v i ccdr [13] data retention current v cc = v dr , ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, or bhe and ble > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ? ? 12 a t cdr [14] chip deselect to data retention time ? 0??ns t r [15] operation recovery time ? 45 ? ? ns data retention waveform figure 2. data retention waveform [16] v cc (min) v cc (min) t cdr v dr > 2.0 v data retention mode t r ce 1 or v cc bhe . ble ce 2 or notes 12. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25 c. 13. chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 14. tested initially and after any design or process changes that may affect these parameters. 15. full device operation requires linear v cc ramp from v dr to v cc (min) > 100 s or stable at v cc (min) > 100 s. 16. bhe . ble is the and of bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling bhe and ble .
cy62167e mobl ? document number: 001-15607 rev. *e page 7 of 17 switching characteristics over the operating range parameter [17, 18] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [19] 5 ? ns t hzoe oe high to high z [19, 20] ? 18 ns t lzce ce 1 low and ce 2 high to low z [19] 10 ? ns t hzce ce 1 high and ce 2 low to high z [19, 20] ? 18 ns t pu ce 1 low and ce 2 high to power-up 0 ? ns t pd ce 1 high and ce 2 low to power-down ? 45 ns t dbe ble/bhe low to data valid ? 45 ns t lzbe ble /bhe low to low z [19, 21] 5 ? ns t hzbe ble /bhe high to high z [19, 20] ? 18 ns write cycle [22] t wc write cycle time 45 ? ns t sce ce 1 low and ce 2 high to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [19, 20] ? 18 ns t lzwe we high to low z [19] 10 ? ns notes 17. test conditions for all parameters other than tristate parame ters assume signal transition time of 1 v/ns, timing reference levels of v cc (typ)/2, input pulse levels of 0 to v cc (typ), and output loading of the specified i ol /i oh as shown in figure 1 on page 5 . 18. in an earlier revision of this device, under a specific application condition, read and write operations were limited to swi tching of the byte enable and/or chip enable signals as described in the application notes an13842 and an66311 . however, the issue has been fixed and in pr oduction now, and hence, these application notes are no longer applicable. they are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in production. 19. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 20. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 21. if both byte enables are toggled together, this value is 10 ns. 22. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenc ed to the edge of the signal that terminates the write.
cy62167e mobl ? document number: 001-15607 rev. *e page 8 of 17 switching waveforms figure 3. read cycle no. 1 (address transition controlled) [23, 24] figure 4. read cycle no. 2 (oe controlled) [24, 25] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes 23. the device is continuously selected. oe , ce 1 = v il , bhe , ble or both = v il , and ce 2 = v ih . 24. we is high for read cycle. 25. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high.
cy62167e mobl ? document number: 001-15607 rev. *e page 9 of 17 figure 5. write cycle no. 1 (we controlled) [26, 27, 28] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 29 ce 1 address ce 2 we data i/o oe bhe /ble notes 26. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be refere nced to the edge of the signal that terminates the write. 27. data i/o is high impedance if oe = v ih . 28. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 29. during this period the i/os are in output state and input signals must not be applied.
cy62167e mobl ? document number: 001-15607 rev. *e page 10 of 17 figure 6. write cycle no. 2 (ce 1 or ce 2 controlled) . [30, 31, 32] figure 7. write cycle no. 3 (we controlled, oe low) [32] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 33 ce 1 address ce 2 we data i/o oe bhe /ble valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 33 ce 1 address ce 2 we data i/o bhe /ble notes 30. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be refere nced to the edge of the signal that terminates the write. 31. data i/o is high impedance if oe = v ih . 32. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 33. during this period the i/os are in output state and input signals must not be applied.
cy62167e mobl ? document number: 001-15607 rev. *e page 11 of 17 figure 8. write cycle no. 4 (bhe /ble controlled, oe low) [34] switching waveforms (continued) t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 35 ce 1 address ce 2 we data i/o bhe /ble notes 34. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 35. during this period the i/os are in output state and input signals must not be applied.
cy62167e mobl ? document number: 001-15607 rev. *e page 12 of 17 truth table ce 1 ce 2 we oe bhe ble inputs outputs mode power hx [36] x x x x high z deselect/power-down standby (i sb ) x [36] l x x x x high z deselect/power-down standby (i sb ) x [36] x [36] x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) read active (i cc ) lhhllhhigh z (i/o 0 ?i/o 7 ); data out (i/o 8 ?i/o 15 ) read active (i cc ) l h h h l h high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) write active (i cc ) lhlxlhhigh z (i/o 0 ?i/o 7 ); data in (i/o 8 ?i/o 15 ) write active (i cc ) note 36. the ?x? (do not care) state for the chip enables in the truth table refers to the logic state (either high or low). intermed iate voltage levels on these pins is not permitted.
cy62167e mobl ? document number: 001-15607 rev. *e page 13 of 17 ordering information the below table lists the cy62167ell key package features and orde ring codes. the table contains only the parts that are curren tly available. if you do not see what you are looking for, contact y our local sales representative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . ordering code definitions speed (ns) ordering code package diagram package type operating range 45 cy62167ell-45zxi 51-85183 48-pin tsop i (pb-free) industrial temperature grade: i = industrial pb-free package type: z = 48-pin tsop i speed grade: 45 ns ll = low power process technology: 90 nm bus width = 16 density = 16-mbit family code: mobl sram family company id: cy = cypress 621 cy 6 7 - ll z e 45 i x
cy62167e mobl ? document number: 001-15607 rev. *e page 14 of 17 package diagram figure 9. 48-pin tsop i (12 18.4 1.0 mm) z48a package outline, 51-85183 51-85183 *c
cy62167e mobl ? document number: 001-15607 rev. *e page 15 of 17 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy62167e mobl ? document number: 001-15607 rev. *e page 16 of 17 document history page document title: cy62167e mobl ? , 16-mbit (1 m 16 / 2 m 8) static ram document number: 001-15607 rev. ecn no. issue date orig. of change description of change ** 1103145 see ecn vkn new data sheet. *a 1138903 see ecn vkn converted from preliminary to final changed i cc(max) spec from 2.8 ma to 4.0 ma for f=1 mhz changed i cc(typ) spec from 22 ma to 25 ma for f=f max changed i cc(max) spec from 25 ma to 30 ma for f=f max added footnote# 8 related to v il changed i ccdr spec from 10 ? a to 12 ? a added footnote# 14 related to ac timing parameters *b 2934385 06/03/10 vkn included bhe , ble in i sb2 , i ccdr test conditions to reflect byte power down feature added footnote #35 related to chip enable updated package diagram updated template *c 3279426 06/10/2011 rame removed the note ?for best practice recommendations, refer to the cypress application note an1064, sram system guidelines.? in page 1 and its reference in functional description . updated switching characteristics (changed the min value of t lzbe parameter). updated in new template. *d 4024137 06/10/2013 memj updated functional description . updated electrical characteristics : added one more test condition ?v cc = 5.5 v, i oh = ?0.1 ma? for v oh parameter and added maximum value corresponding to that test condition. added note 8 and referred the same note in maximum value for v oh parameter corresponding to test condition ?v cc = 5.5 v, i oh = ?0.1 ma?. updated package diagram : spec 51-85183 ? changed revision from *b to *c. *e 4101995 08/22/2013 vini updated switching characteristics : updated note 18. updated in new template.
document number: 001-15607 rev. *e revised august 22, 2013 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62167e mobl ? ? cypress semiconductor corporation, 2007-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

▲Up To Search▲

Price & Availability of CY62167ELL-45ZXIT

	To Download CY62167ELL-45ZXIT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .